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INTEGRATED CIRCUITS
74F113 Dual J-K negative edge-triggered flip-flops without reset
Product specification IC15 Data Handbook 1991 Feb 14
Philips Semiconductors
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
FEATURE
* Industrial temperature range available (-40C to +85C)
DESCRIPTION
The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high and flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP. TYPE 74F113 TYPICAL fmax 100MHz
PIN CONFIGURATION
CP0 K0 J0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC CP1 K1 J1 SD1 Q1 Q1
SF00140
TYPICAL SUPPLY CURRENT (TOTAL) 15mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F113N N74F113D INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F113N I74F113D PKG. DWG. #
14-pin plastic DIP 14-pin plastic SO
SOT27-1 SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS J0, J1 K0, K1 CP0, CP1 SD0, SD1 Q0, Q1, Q0, Q1 J inputs K inputs Clock inputs (active falling edge) Set inputs (active low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/4.0 1.0/5.0 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/2.4mA 20A/3.0mA 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
3 11 2 12
IEC/IEEE SYMBOL
3 1J J0 1 4 13 10 CP0 SD0 CP1 SD1 Q0 Q0 Q1 Q1 11 13 C2 12 10 VCC = Pin 14 GND = Pin 7 5 6 9 8 2K 2S 8 2J 9 4 J1 K0 K1 1 C1 2 1K 1S 6 5
SF00141
SF00142
1996 Mar 14
2
853-0339 16575
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS SD CP X J X h h l l K X h l h l OUTPUTS OPERATING MODE Q H q H L q Q L q L H q Asynchronous set Toggle Load "1" (set) Load "0" (reset) Hold 'no change"
Q
5, 9
6, 8 Q
L H
SD K
4, 10 2, 12 3, 11 J
H H
VCC = Pin 14 GND = Pin 7
1, 13 CP
H
SF00143
NOTES: H = High-voltage level h = High-voltage level one setup time prior to high-to-low clock transition L = Low-voltage level l = Low-voltage level one setup time prior to high-to-low clock transition q = Lower case indicate the state of the referenced output prior to the high-to-low clock transition X = Don't care = high-to-low clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Commercial range Operating free-air temperature range free air Storage temperature range Industrial range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -40 to +85 -65 to +150 UNIT V V mA V mA C C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Commercial range Operating free-air temperature range free air Industrial range 0 -40 PARAMETER MIN 4.5 2.0 0.8 -18 -1 20 +70 +85 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C C
1996 Mar 14
3
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V Jn, Kn IIL IOS Low-level input current Short-circuit output current3 current4 CPn SDn VCC = MAX -60 VCC = MAX, VI = 0.5V LIMITS MIN TYP2 MAX UNIT V 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -0.6 -2.4 -3.0 -150 V V V V A A mA mA mA mA
VO OH
High-level High level output voltage
IO = MAX OH
10%VCC 5%VCC 10%VCC 5%VCC
2.5 2.7
VO OL VIK II IIH
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current
IO = MAX OL
ICC Supply (total) VCC = MAX 15 21 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF RL = 500 MIN fmax tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn, to Qn or Qn Waveform 1 Waveform 1 Waveform 2 85 2.0 2.0 2.0 2.0 TYP 100 4.0 4.0 4.5 4.5 6.0 6.0 6.5 6.5 MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF RL = 500 MIN 80 2.0 2.0 2.0 2.0 7.0 7.0 7.5 7.5 MAX VCC = +5.0V 10% Tamb = -40C to +85C CL = 50pF RL = 500 MIN 80 2.0 2.0 2.0 2.0 7.5 7.0 8.0 7.5 MAX ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25C CL = 50pF RL = 500 MIN tsu (H) tsu(L) th (H) th (L) tw (H) tw (L) tw (L) trec Setup time, high or low Jn, Kn to CPn Hold time, high or low Jn, Kn to CPn CP pulse width, high or low SDn pulse width, low Recovery time SDn to CPn Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 2 4.0 3.5 0.0 0.0 4.5 4.5 4.5 4.5 TYP MAX VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF RL = 500 MIN 5.0 4.0 0.0 0.0 5.0 5.0 5.0 5.0 MAX VCC = +5.0V 10% Tamb = -40C to +85C CL = 50pF RL = 500 MIN 5.0 4.5 0.0 0.0 5.0 5.0 5.0 5.0 MAX ns ns ns ns ns UNIT
1996 Mar 14
4
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
Kn Jn, Kn VM VM th(L) = 0 1/fmax CPn VM tw(L) VM tw(H) VM tPHL Qn VM VM tPHL VM tPLH VM VM Jn VM th(H) = 0
Jn tsu(L)
Kn tsu(H)
tPLH Qn
SF00144
Waveform 1.
Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Width, and Maximum Clock Frequency
Jn, Kn
SDn VM
tw(L)
VM trec
CPn tPLH Qn VM tPHL Qn VM
VM
SF00145
Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock
1996 Mar 14
5
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1996 Mar 14
6
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
1996 Mar 14
7
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1996 Mar 14
8
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
NOTES
1996 Mar 14
9
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05072
Philips Semiconductors
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